module dtube_control(
    input clk,
    input rst_n,
    
    input [11:0] data_time,
    
    output reg [5:0] data_sel,
    output reg [7:0] data_seg
);

reg [9:0] dtube_clk_cnt;
reg dtube_clk;

always @ (posedge clk, negedge rst_n)
begin
    if (!rst_n) begin
        dtube_clk_cnt <= 10'd0;
        dtube_clk <= 1'd0;
    end
    else if (dtube_clk_cnt < 10'd50000) begin
        dtube_clk_cnt <= dtube_clk_cnt + 1'd1;
    end
    else begin
        dtube_clk_cnt <= 10'd0;
        dtube_clk <= ~ dtube_clk;
    end

end

reg [2:0] dtube_cnt;
always @ (posedge dtube_clk, negedge rst_n)
begin
    if (!rst_n) begin
        dtube_cnt <= 3'd0;
    end
    else if (dtube_cnt <= 3'd4)begin
        dtube_cnt <= dtube_cnt + 1'd1;
    end
    else begin
        dtube_cnt <= 3'd0;
    end
end

reg [3:0] digital;
always @ (posedge clk, negedge rst_n)
begin
    if (!rst_n) begin
        digital <= 4'd0;
        data_sel <= 6'd1000_0000;
    end
    else begin
        case (dtube_cnt)
            3'd0:   begin   digital <= (data_time % 60) % 10;     data_sel <= 6'b111110; end
            3'd1:   begin   digital <= (data_time % 60) / 10;     data_sel <= 6'b111101; end
            3'd2:   begin   digital <= 4'd11;                     data_sel <= 6'b111011; end
            3'd3:   begin   digital <= (data_time / 60) % 10;     data_sel <= 6'b110111; end
            3'd4:   begin   digital <= (data_time / 60) / 10;     data_sel <= 6'b101111; end
            default: begin  digital <= 4'd0;                      data_sel <= 6'b111111; end        
        endcase
    end

end




/* */
always @(posedge clk, negedge rst_n)
begin
    if (!rst_n)
        data_seg <= 4'd0;
    else begin
        case (digital)
            4'd0 : data_seg <= 8'b11000000;   // 0
            4'd1 : data_seg <= 8'b11111001;   // 1
            4'd2 : data_seg <= 8'b10100100;   // 2
            4'd3 : data_seg <= 8'b10110000;   // 3
            4'd4 : data_seg <= 8'b10011001;   // 4
            4'd5 : data_seg <= 8'b10010010;   // 5
            4'd6 : data_seg <= 8'b10000010;   // 6
            4'd7 : data_seg <= 8'b11111000;   // 7
            4'd8 : data_seg <= 8'b10000000;   // 8
            4'd9 : data_seg <= 8'b10010000;   // 9
            4'd10: data_seg <= 8'b11111111;   //
            4'd11: data_seg <= 8'b10111111;   // (-)
            default: 
                   data_seg <= 8'b10000000;
        endcase
    end
end



endmodule


/* module inst

dtube_control dtube_control_inst
(
    .clk            (),
    .rst_n          (),
    
    .data_time      (),
    
    .data_sel       (),
    .data_seg       ()
);





*/
